1. Field of the Invention
This invention relates generally to the field of high frequency integrated circuits.
2. Description of the Related Art
High frequency microwave-range integrated circuits (ICs) based on gallium arsenide (GaAs) are known. Lower frequency-range integrated circuits which include components fabricated on silicon (Si) are also known. It would be highly desirable to extend the high frequency performance capacity of GaAs-based ICs to Si-based ICs, using materials and equipment which are adaptations of those whose use is well established in silicon processing.
Silicon technology has been the foundation of the microelectronics industry, but in attempts to extend the more mature silicon technology to the integration of high frequency microwave components such as coplanar transmission lines and inductors, the inherent limitation of the resistivity of silicon, which is maximal in pure silicon, has been a barrier to fabricating Si-based devices which are technically noncompetitive with GaAs in the microwave range. For example, loss at about 10 GHz on silicon is approximately 20 times that on GaAs; GaAs-based microwave structures have the low loss tangent that would be desirable to achieve in manufacturable Si-based structures. Manufacturability requires processes and results that are stable, predictable, reproducible and cost effective. High frequency devices based on GaAs are relatively more expensive to fabricate than are lower frequency devices based on Si, but lower frequency devices based on Si can be fabricated by processes that produce stable, predictable and reproducible results.
U.S. Pat. No. 5,528,209 issued Jun. 18, 1996 to Mcdonald et al. describes a silicon-based high frequency monolithic structure in which the high frequency transmission lines are fabricated by electroplating gold. Gold plating may give rise to problems such as cost, added process steps to create barriers to electromigration of gold into copper and handling and disposal of the gold electroplating baths and rinses. The present invention does not include gold processing. Rather, wet electroprocessing is avoided by using sputter deposition and sputter cleaning and ashing. The ""209 patent describes via fabrication by reactive ion etching (RIE). In the present invention, via (through-hole) photolithography, including wet or reactive ion etching (RIE) is avoided in fabricating internal vias by using laser ablation, a process which provides superior control of the critical via dimension of slope angle. The ""209 patent uses benzocyclobutene (RCR) resin, which was found not to laser well for the purposes of the present invention. The polyimide (PI) used in the present invention has the advantages of lasering well, low dielectric constant, low moisture absorbency, ability to be applied and cured in a layer up to at least 15 microns thick, and ability to withstand the temperature required to solder or wire bond the completed device without cracking. A paper presented at the 1995 IEEE conference, xe2x80x9cHigh Performance Microwave Elements for SiGe MMICsxe2x80x9d by Michael Case et al. describes a Si-based microwave device using BCB, a resinous composition used in the prepreg art, as the dielectric material. BCB was found to be unsuitable for the processing of the present invention, particularly with respect to laser processing.
An article by Anthony Cataldo and Ron Wilson beginning on page 1 in the Electronic Engineering Times dated Jan. 26, 1988 describes some of the IBM activity in the area of SiGe-based RF ICs.
xe2x80x9cLow-Loss Microwave Transmission Lines and Inductors Implemented in a Manufacturable Si/SiGe HBT Processxe2x80x9d by David C. Laney, Lawrence E. Larson, John Malinowski, David Harame, Seshu Subanna, Rich Volant, Michael Case and Paul Chan was orally presented in September, 1998 at the BCTM meeting in Minnesota. In it are described experimental results of measurements made for square planar inductors and microstrip transmission lines for standard Si VLSI structures having CuAl metallization and thick polyimide dielectric. The work indicates the manufacturability in Si VLSI technology of these lines and inductors and predicts their use in high performance, low cost Si-based 5-10 GHz MMICs in the future.
U.S. Pat. No. 4,830,706 issued May 16, 1989 to Ronald S. Horwath et al. describes one method, not involving laser, in which slope-walled vias with rounded corners are fabricated by finally curing a resinous insulating material in which, after a preliminary partial cure, the via walls had been conventionally straight and corners square. The patent describes problems associated with straight-walled vias and benefits of slope-walled vias and rounding at the intersection of via wall and planar surface.
None of the references anticipates the process and article of manufacture of the present invention.
Accordingly, it is an object of the invention to provide a silicon-based integrated circuit structure having the high frequency performance characteristic of GaAs-based structures. It is a further object of the invention to provide a high frequency silicon-based integrated circuit structure having the performance characteristics of high frequency GaAs-based structures, in which the processing steps and equipment employed are compatible with the processing steps and equipment employed in existing silicon technology processing, and for which the overall cost of manufacture is market competitive.
These and other objects are accomplished in the present invention, wherein a silicon-based high frequency integrated circuit structure includes a dielectric resin separating the signal lines. The substrate is typical of that used in Si-based back-end-of-line (BEOL) IC fabrication, metal deposition in the fabrication of elements such as inductors, transmission lines and capacitors is efficiently performed by vacuum deposition of non-precious metals, and via fabrication is performed by laser ablation rather than by wet processing or RIE in thick polyimide dielectric of a type used also in non-microwave applications Use of the laser enables the fabrication of predictably and reproducibly smooth and even slope-walled vias on which continuous metallization can be deposited despite the thickness of the dielectric.
The number of processing steps in the present invention is reduced compared to the art, and the number of wet processing steps is minimized. The resulting silicon-based modular structure can incorporate numerous integrated high quality passive microwave lines and components and a ground plane fabricated in BEOL metallurgy. Structures can be built with or without a ground plane, depending upon the application. It is high frequency performance competitive with GaAs-based structures and is cost competitive with silicon-based structures. It is useful in applications and markets such as, for example, tuned matching networks, reactive loading, power splitters, transistors, inductors, transmission lines, resonators, couplers, analog, mixed signal, RF, communications, impedance transformers, monolithic microwave integrated circuit (MMIC) interconnects and like microwave elements.
Advantages include the provision in transmission line structures of low loss compared to BEOL Si-based structures; self-resonant frequency beyond GaAs while showing significant Q factor improvement compared to BEOL; Si enabling process for RADAR (20 GHz) applications which otherwise cannot have integrated passive elements; and provision of high level of integration (BiCMOS) for GaAs. The modularity of the structure of the present invention permits the addition of high frequency microwave receive/transmit capability to be mounted to existing products on Si, SiGe, GaAs and other semiconductor substrates.
In one embodiment of the present invention, a SiGe wafer is processed normally through solid conducive terminal via formation. Polyimide (PI) 5811, a product of E.I.Dupont et Nemours and Co. of Delaware, in an amount sufficient to result in a cured layer of nominally 15 microns, is spun on and cured on the wafer at about 400 degrees C. Laser ablation is performed on the cured PI down to each terminal stud via to create a rounded slope-walled via of about 62 degrees. Between the SiGe and the polyimide is TV dielectric, which comprises a silicon oxide/nitride sandwich layer. Ashing the ablated via in an oxygen-containing plasma by RIE, optionally followed by sputter etching, assures the removal from the slope-walled via of any debris left behind by the laser. A via at its narrowest width is about 10 microns in diameter. Next a top metallization layer about 2 microns to about 2.5 microns thick of AlCu is sputter deposited over the PI, including along the sloped walls and the bottom of the terminal stud via, for electrical communication between transmission lines. The AlCu metallurgy can be about 0.2% to about 5.0% by weight of Cu. After photolithography a top metal etch shapes the transmission lines. A second layer of resist is spun onto the structure and cured to a thickness of about 3 microns and xe2x80x9cball viasxe2x80x9d are fabricated to provide electrical communication with the transmission lines at predetermined locations. Whereas the layer of thick polyimide need not be photoactive because the topography is shaped by laser rather than by photolithography, the second layer of polyimide can be photoactive since it is thin enough to be patterned photolithographically rather than by laser. PbSn solder is applied at the ball via, reflowed and cooled to form a ball of solder for subsequent controlled collapse chip connection (C4) to a customer-defined package. Wire bonding is an alternate to C4 bonding.
In order to facilitate further understanding of the present invention, reference is made to the following detailed description taken in conjunction with the drawings: